View S93VP463P-27_7926120.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

summit microelectronics, inc. ? 300 orchard city drive, suite 131 ? campbell, ca 95008 ? telephone 408-378- 6461 ? fax 408-378-6586 ? www.summitmicro.com 1 s93vp462/s93vp463 ?summit microelectronics, inc. 1998 2040-01 10/23/98 characteristics subject to change without notice voltage-sense write protected memory features voltage-sense write protection low v cc write lockout all writes inhibited when v cc < v trip protects against inadvertent writes during - power-up - power-down - brown-out conditions all devices ?eadable?from 1.8v to 5.5v - user selectable v trip levels memory 1k-bit microwire memory s93vp462 internally ties org low 100% compatible with all 8-bit implementations sixteen byte page write capability s93vp463 internally ties org high 100% compatible with all 16-bit implementations eight word page write capability applications new designs for applications where data corruption cannot be permitted. replacement of existing industry standard 1k memories. overview the s93vp462 and s93vp463 are voltage monitoring memory devices that write protect the array from inad- vertent writes whenever v cc is below v trip . both devices have 1k-bits of e 2 prom memory that is accessible via the industry standard microwire bus. the s93vp462 is configured with an internal org pin tied low providing a 8-bit byte organization and the s93vp463 is configured with an internal org pin tied high providing a 16-bit word organization. both the s93vp462 and s93vp463 have page write capability. the devices are designed for a minimum 1,000,000 program/erase cycles and have data retention in ex- cess of 100 years. block diagram gnd + - v cc 8 v trip cs di do data i/o mode decode write control circuitry sk 1 2 3 4 5 i reset pulse generator nonvolatile memory array 6 7 nc nc 2040 ill2.0
2 s93vp462/s93vp463 2040-01 10/23/98 pin functions pin name function cs chip select sk clock input di serial data input do serial data output v cc +2.7 to 6.0v power supply gnd ground nc no connect pin configuration dip package (p) soic package (s) device operation write lockout description the s93vp462/vp463 provides a precision internal reset controller that ensures correct system operation during brown-out and power-up/-down conditions. during power-up, the write lockout remains active until v cc reaches the v trip threshold. write lockout will continue to be driven for approximately 150 ms after v cc reaches v trip . during power-down, write lockout will be driven active when even v cc falls below v trip . general operation the s93vp462/vp463 is a 1024-bit nonvolatile memory intended for use with industry standard microproces- sors. the s93vp463 is organized as x16, seven 9-bit instructions control the reading, writing and erase operations of the device. the s93vp462 is organized as x8, seven 10-bit instructions control the reading, writing and erase operations of the device. the device operates on a single 3v or 5v supply and will generate on chip, the high voltage required during any write operation. instructions, addresses, and write data are clocked into the di pin on the rising edge of the clock (sk). the do pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. the ready/busy status can be determined after the start of a write operation by selecting the device (cs high) and polling the do pin; do low indicates that the write operation is not completed, while do high indicates that the device is ready for the next instruction. see the applications aid section for detailed use of the ready busy status. the format for all instructions is: one start bit; two op code bits and either six (x16) or seven (x8) address or instruction bits. 2040 ill1.0 cs sk di do v cc nc nc gnd 1 2 3 4 8 7 6 5 cs sk di do v cc nc nc gnd 1 2 3 4 8 7 6 5
3 s93vp462/s93vp463 2040-01 10/23/98 read upon receiving a read command and an address (clocked into the di pin), the do pin of the s93vp462/ vp463 will come out of the high impedance state and, will first output an initial dummy zero bit, then begin shifting out the data addressed (msb first). the output data bits will toggle on the rising edge of the sk clock and are stable after the specified time delay (t pd0 or t pd1 ). write after receiving a write command, address and the data, the cs (chip select) pin must be deselected for a minimum of 250ns (t csmin ). the falling edge of cs will start automatic erase and write cycle to the memory location specified in the instruction. the ready/busy status of the s93vp462/vp463 can be determined by selecting the device and polling the do pin. erase upon receiving an erase command and address, the cs (chip select) pin must be deselected for a minimum of 250ns (t csmin ). the falling edge of cs will start the auto erase cycle of the selected memory location. the ready/busy status of the s93vp462/vp463 can be determined by selecting the device and polling the do pin. once cleared, the content of a cleared location returns to a logical ??state. figure 1. sychronous data timing figure 2. read instruction timing sk 2040 ill 3.0 di cs do t dis t pd0, t pd1 t csmin t css t dis t dih t skhi t csh valid valid data v alid t sklow sk 2040 ill4.0 cs di do t cs standby t hz high-z high-z 11 0 a n a n? a 0 0 d n d n? d 1 d 0 t pd0
4 s93vp462/s93vp463 2040-01 10/23/98 erase/write enable and disable the s93vp462/vp463 powers up in the write disable state. any writing after power-up or after an ewds (write disable) instruction must first be preceded by the ewen (write enable) instruction. once the write in- struction is enabled, it will remain enabled until power to the device is removed, or the ewds instruction is sent. the ewds instruction can be used to disable all s93vp462/vp463 write and clear instructions, and will prevent any accidental writing or clearing of the device. data can be read normally from the device regardless of the write enable/disable status. erase all upon receiving an eral command, the cs (chip select) pin must be deselected for a minimum of 250ns (t csmin ). the falling edge of cs will start the self clocking clear cycle of all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the s93vp462/vp463 can be determined by selecting the device and polling the do pin. once cleared, the contents of all memory bits will be in a logical ??state. write all upon receiving a wral command and data, the cs (chip select) pin must be deselected for a minimum of 250ns (t csmin ). the falling edge of cs will start the self clocking data write to all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/ busy status of the s93vp462/vp463 can be determined by selecting the device and polling the do pin. it is not necessary for all memory locations to be cleared before the wral command is executed. page write 93462 - assume wen has been issued. the host will then take cs high, and begin clocking in the start bit, write command and 7-bit address immediately fol- lowed by the first byte of data to be written. the host can then continue clocking in 8-bit bytes of data with each byte to be written to the next higher address. internally the address pointer is incremented after receiving each group of eight clocks; however, once the address counter reaches xxx 1111 it will roll over to xxx 0000 with the next clock. after the last bit is clocked in no internal write operation will occur until cs is brought low. 93463 - assume wen has been issued. the host will then take cs high, and begin clocking in the start bit, write command and 6-bit address immediately followed by the first 16-bit word of data to be written. the host can then continue clocking in 16-bit words of data with each word to be written to the next higher address. internally the address pointer is incremented after receiving each group of sixteen clocks; however, once the address counter reaches xxx x111 it will roll over to xx x000 with the next clock. after the last bit is clocked in no internal write operation will occur until cs is brought low. continuous read this begins just like a standard read with the host issuing a read instruction and clocking out the data byte [word]. if the host then keeps cs high and continues generating clocks on sk, the s93vp462/ vp463 will output data from the next higher address location. the s93vp462/vp463 will continue incrementing the address and outputting data so long as cs stays high. if the highest address is reached, the address counter will roll over to address 0000. cs going low will reset the instruction register and any subsequent read must be initiated in the normal man- ner of issuing the command and address.
5 s93vp462/s93vp463 2040-01 10/23/98 figure 3. write instruction timing figure 4. erase instruction timing figure 5. ewen/ewds instruction timing sk 2040 ill 5.0 cs di do t cs standby high-z high-z 101 a n a n-1 a 0 d n d 0 busy ready status verify t sv t hz t ew sk 2040 ill6.0 cs di do standby high-z high-z 1 a n a n-1 busy ready status verify t sv t hz t ew t cs 11 a 0 sk 2040 ill 7.0 cs di standby 10 0 * * enable=1 1 disable=00
6 s93vp462/s93vp463 2040-01 10/23/98 figure 7. wral instruction timing instruction set instruction start opcode address data comments bit x8 x16 x8 x16 read 1 10 a6?0 x(a5?0) read address an?0 erase 1 11 a6?0 x(a5?0) clear address an?0 write 1 01 a6?0 x(a5?0) d7?0 d15?0 write address an?0 ewen 1 00 11xxxxx 11xxxx write enable ewds 1 00 00xxxxx 00xxxx write disable eral 1 00 10xxxxx 10xxxx clear all addresses wral 1 00 01xxxxx 01xxxx d7?0 d15?0 write all addresses 2040 pgm t5.0 figure 6. eral instruction timing sk 2040 ill 8.0 cs di do t cs high-z high-z 10 1 busy ready status verify t sv t hz t ew 00 standby sk 2040 ill 10.0 cs di do t cs high-z 10 1 busy ready status verify t sv t hz t ew 0 0 standby d o d n
7 s93vp462/s93vp463 2040-01 10/23/98 absolute maximum ratings* temperature under bias ......................................................................................................... ........................... 55 c to +125 c storage temperature ............................................................................................................ ............................. 65 c to +150 c voltage on any pin with respect to ground (1) ............................................................................................. ?.0v to +v cc +2.0v v cc with respect to ground ........................................................................................................ .......................... ?.0v to +7.0v package power dissipation capability (ta = 25 c) ............................................................................................................. 1.0w lead soldering temperature (10 secs) ........................................................................................... ................................... 300 c output short circuit current (2) ............................................................................................................................... ............ 100 ma *comment stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specificat ion is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. note: (1) the minimum dc input voltage is ?.5v. during transitions, inputs may undershoot to ?.0v for periods of less than 20 ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from ?v to v cc +1v. d.c. operating characteristics (over recommended operating conditions unless otherwise specified) limits symbol parameter min. typ. max. units test conditions i cc power supply current 3 ma di = 0.0v, f sk = 1mhz (operating) v cc = 5.0v, cs = 5.0v, output open i sb power supply current 50 a cs = 0v (standby) reset outputs open i li input leakage current 2 av in = 0v to v cc i lo output leakage current 10 av out = 0v to v cc , (including org pin) cs = 0v v il1 input low voltage -0.1 0.8 v 4.5v v cc <5.5v v ih1 input high voltage 2 v cc +1 v v il2 input low voltage 0 v cc x0.2 v 1.8v v cc <2.7v v ih2 input high voltage v cc x0.7 v cc +1 v v ol1 output low voltage 0.4 v 4.5v v cc <5.5v v oh1 output high voltage 2.4 v i ol = 2.1ma i oh = -400 a v ol2 output low voltage 0.2 v 1.8v v cc <2.7v v oh2 output high voltage v cc -0.2 v i ol = 1ma i oh = -100 a 2040 pgm t3.0 reliability characteristics symbol parameter min. max. units reference test method n end (3) endurance 1,000,000 cycles/byte mil-std-883, test method 1033 t dr (3) data retention 100 years mil-std-883, test method 1008 v zap (3) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (3)(4) latch-up 100 ma jedec standard 17 2040 pgm t2.0 temperature min max commercial 0 c +70 c industrial -40 c +85 c recommended operating conditions 2040 pgm t7.0
8 s93vp462/s93vp463 2040-01 10/23/98 limits v cc =2.7v-4.5v v cc =4.5v-5.5v test symbol parameter min. max. min. max. units conditions t css cs setup time 100 50 ns t csh cs hold time 0 0 ns v il = 0.45v t dis di setup time 200 100 ns v ih = 2.4v t dih di hold time 200 100 ns c l = 100pf t pd1 output delay to 1 0.5 0.25 sv ol = 0.8v t pd0 output delay to 0 0.5 0.25 sv oh = 2.0v t hz (1) output delay to high-z 200 100 ns t ew program/erase pulse width 10 10 ms t csmin minimum cs low time 0.5 0.25 s t skhi minimum sk high time 0.5 0.25 s t sklow minimum sk low time 0.5 0.25 s t sv output delay to status valid 0.5 0.25 sc l = 100pf sk max maximum clock frequency dc 500 dc 1000 khz note: (1) this parameter is tested initially and after a design or process change that affects the parameter. note: (1) this parameter is tested initially and after a design or process change that affects the parameter. a.c. characteristics (over recommended operating conditions unless otherwise specified) c l = 100pf 2040 pgm t6.0 pin capacitance symbol test max. units conditions c out (1) output capacitance (do) 5 pf v out =ov c in (1) input capacitance (cs, sk, di, org) 5 pf v in =ov 2040 pgm t4.0
9 s93vp462/s93vp463 2040-01 10/23/98 t puw t glitch t ldly v lock v cc t puw t ldly v lockout v lockout v lockout internal action 2040 ill9.0 figure 8. v lock timing diagram 2019 pgm t1 1.3
10 s93vp462/s93vp463 2040-01 10/23/98 .228 (5.80) .244 (6.20) .016 (.40) .035 (.90) .020 (.50) .010 (.25) x45 .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) typ. .275 (6.99) typ. .030 (.762) typ. 8 places .050 (1.27) typ. .050 (1.270) typ. 8 places .157 (4.00) .150 (3.80) .196 (5.00) 1 .189 (4.80) footprint 8pn jedec soic ill.2 .375 (9.525) pin 1 indicator .015 (.381) min. .130 (3.302) .100 (2.54) typ. .018 (.457) typ. .060 .005 (1.524) .127 typ. .130 (3.302) seating plane .070 (1.778) .0375 (0.952) .300 (7.620) 5 -7 typ. (4 plcs) .350 (8.89) .009 .002 (.229 .051) 0 -15 .250 (6.350) 8pn pdip/p ill.3 8 pin soic (type s) package jedec (150 mil body width) 8 pin pdip (type p) package
11 s93vp462/s93vp463 2040-01 10/23/98 ready/busy status during the internal write operation the s93vp462/vp463 memory array is inaccessible. after starting the write operation (taking cs low) the host can implement a 10ms timeout routine or alternatively it can employ a polling routine that tests the state of the do pin. after starting the write, testing for the status is easily accomplished by taking cs high and testing the state of do. if it is low the device is still busy with the internal write. if it is high the write operation has completed. for the polling routine the host has the option of toggling cs for each test of do, or it can place cs high and then intermittently test do. sk is not required for any of these operations. once the device is ready, it will continue to drive do high whenever the s93vp462/vp463 is selected. the ready state of do can be cleared by clocking in a start bit; this start bit can either be the beginning of a new command sequence or it can be a dummy start bit with cs returning low before the host issues a new command. sk 2040 ill13.0 cs di do t cs high-z high-z status cleared busy ready status verify t sv t hz t ew
12 s93vp462/s93vp463 2040-01 10/23/98 notice summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to impr ove design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits describ ed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user? specific application. while the information in this publication has been carefully checked, summit microelectronics, i nc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect it s safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives writte n assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks ; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. voltage-sense and voltage-sense are trademarks of summit microelectronics, inc. ?copyright 1998 summit microelectronics, inc. ordering information s93vp463 base part number s93vp463 = 16-bit configuration s93vp462 = 8-bit configuration tape and reel option blank = tube t = tape and reel package p = 8 lead pdip s = 8 lead 150mil soic operating voltage range a = 4.5v to 5.5v v trip min. @ 4.25v b = 4.5v to 5.5v v trip min. @ 4.50v 2.7 = 2.7v to 5.5v v trip min. @ 2.55v p -2.7 t 2040 ill11.0

▲Up To Search▲

Price & Availability of S93VP463P-27

	To Download S93VP463P-27 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .